Transcript
------------------------------------------------------------------------------------------,
-- Universidade Federal do Rio Grande do Sul --,
-- Pos-graduacao em Ciencia da Computacao --,
-- Circuito gerador de endere os crescentes --,
-- Sa das para 3 endere os de 5 bits (filtro com 32 taps) --,
-- Por Denis Franco em janeiro de 1999 --,
------------------------------------------------------------------------------------------,
,
library ieee;,
use ieee.std_logic_arith.all;,
,
library ieee;,
use ieee.std_logic_1164.all;,
,
entity ender is,
port (,
clock : in bit; -- Sinal de sincronismo,
rst : in bit; -- Sinal de inicializa o,
hab1 : in bit; -- Sinal de incremento do endere o 1,
ender1 : out std_logic_vector(4 downto 0); -- Endere o 1,
hab2 : in bit; -- Sinal de incremento do endere o 2,
ender2 : out std_logic_vector(4 downto 0); -- Endere o 2 ,
hab3 : in bit; -- Sinal de incremento do endere o 3,
ender3 : out std_logic_vector(4 downto 0) -- Endere o 3,
);,
,
end ender;,
,
architecture Sender of ender is,
,
signal end1: integer range 0 to 31;,
signal end2: integer range 0 to 31;,
signal end3: integer range 0 to 31;,
,
begin,
,
-- Processo de controle do endere o 1,
process(clock, hab1)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then ,
if hab1 = '1' then,
end1 <= end1 + 1;,
else,
end1 <= end1;,
end if;,
else,
end1 <= 0;,
end if;,
end if;,
end process;,
,
-- Processo de controle do endere o 2,
process(clock, hab2)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then,
if hab2 = '1' then,
end2 <= end2 + 1;,
else,
end2 <= end2;,
end if;,
else,
end2 <= 0;,
end if;,
end if;,
end process;,
,
-- Processo de controle do endere o 3,
process(clock, hab3)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then,
if hab3 = '1' then,
end3 <= end3 + 1;,
else,
end3 <= end3;,
end if;,
else,
end3 <= 0;,
end if;,
end if;,
end process;,
,
-- Convers o de dados do tipo inteiro para std_logic_vector ,
ender1 <= conv_std_logic_vector(end1,5);
ender2 <= conv_std_logic_vector(end2,5);
ender3 <= conv_std_logic_vector(end3,5);
,
end Sender;,
,
,
,
-- Circuito gerador de endere os crescentes --,
-- Sa das para 3 endere os de 5 bits (filtro com 32 taps) --,
-- Por Denis Franco em janeiro de 1999 --,
------------------------------------------------------------------------------------------,
,
library ieee;,
use ieee.std_logic_arith.all;,
,
library ieee;,
use ieee.std_logic_1164.all;,
,
entity ender is,
port (,
clock : in bit; -- Sinal de sincronismo,
rst : in bit; -- Sinal de inicializa o,
hab1 : in bit; -- Sinal de incremento do endere o 1,
ender1 : out std_logic_vector(4 downto 0); -- Endere o 1,
hab2 : in bit; -- Sinal de incremento do endere o 2,
ender2 : out std_logic_vector(4 downto 0); -- Endere o 2 ,
hab3 : in bit; -- Sinal de incremento do endere o 3,
ender3 : out std_logic_vector(4 downto 0) -- Endere o 3,
);,
,
end ender;,
,
architecture Sender of ender is,
,
signal end1: integer range 0 to 31;,
signal end2: integer range 0 to 31;,
signal end3: integer range 0 to 31;,
,
begin,
,
-- Processo de controle do endere o 1,
process(clock, hab1)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then ,
if hab1 = '1' then,
end1 <= end1 + 1;,
else,
end1 <= end1;,
end if;,
else,
end1 <= 0;,
end if;,
end if;,
end process;,
,
-- Processo de controle do endere o 2,
process(clock, hab2)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then,
if hab2 = '1' then,
end2 <= end2 + 1;,
else,
end2 <= end2;,
end if;,
else,
end2 <= 0;,
end if;,
end if;,
end process;,
,
-- Processo de controle do endere o 3,
process(clock, hab3)
begin,
if (clock = '0' and not clock'stable) then,
if rst = '0' then,
if hab3 = '1' then,
end3 <= end3 + 1;,
else,
end3 <= end3;,
end if;,
else,
end3 <= 0;,
end if;,
end if;,
end process;,
,
-- Convers o de dados do tipo inteiro para std_logic_vector ,
ender1 <= conv_std_logic_vector(end1,5);
ender2 <= conv_std_logic_vector(end2,5);
ender3 <= conv_std_logic_vector(end3,5);
,
end Sender;,
